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sunjin-choi/svwdm

github.com/sunjin-choi/svwdm ↗

SystemVerilog

Stars

⭐ 0

PRs Reviewed

1

Bot Comments

4

Primary Language

SystemVerilog

Merge Rate

100.0%

Avg Time to Merge

3h

Avg Additions

+515

Avg Deletions

-6

Avg Files Changed

25

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