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sourav-bhongade/Custom-8-Bit-CPU-in-Verilog-Minimal-RISC-Like-Architecture
github.com/sourav-bhongade/Custom-8-Bit-CPU-in-Verilog-Minimal-RISC-Like-Architecture ↗Verilog
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Primary Language
Verilog
Merge Rate
100.0%
Avg Time to Merge
30m
Avg Additions
+1.1K
Avg Deletions
-179
Avg Files Changed
11
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