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openhwgroup/cvw-arch-verif

github.com/openhwgroup/cvw-arch-verif ↗

SystemVerilog

Stars

⭐ 18

PRs Reviewed

1

Bot Comments

4

Primary Language

SystemVerilog

Merge Rate

100.0%

Avg Time to Merge

5h

Avg Additions

+356

Avg Deletions

-843

Avg Files Changed

33

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