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kornelu123/risc-v-sv

github.com/kornelu123/risc-v-sv ↗

SystemVerilog

Stars

⭐ 0

PRs Reviewed

2

Bot Comments

15

Primary Language

SystemVerilog

Merge Rate

50.0%

Avg Time to Merge

36m

Avg Additions

+368

Avg Deletions

-26

Avg Files Changed

9

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