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chipsalliance/caliptra-rtl

github.com/chipsalliance/caliptra-rtl ↗

SystemVerilog

Stars

⭐ 147

PRs Reviewed

12

Bot Comments

52

Primary Language

SystemVerilog

Merge Rate

75.0%

Avg Time to Merge

11d

Avg Additions

+3.3K

Avg Deletions

-177

Avg Files Changed

38

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12 PRs19 events