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Tarek-Eletriby/AXI4_Verification

github.com/Tarek-Eletriby/AXI4_Verification ↗

SystemVerilog

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0

Primary Language

SystemVerilog

Merge Rate

100.0%

Avg Time to Merge

1h

Avg Additions

+18

Avg Deletions

-16

Avg Files Changed

1

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